1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and, more particularly, it relates to a hybrid LSI having a combination of bipolar/CMOS transistors.
2. Description of the Related Art
It has been generally recognized that a major disadvantage of a semiconductor device having a CMOS feature is that parasitic circuits are inevitably produced to give rise to a latch-up phenomenon. Nevertheless, the semiconductor device of this type has been attracting attention in the field of LSI technology because of its low energy consumption level. A BiCMOS LSI is particularly advantageous because it include the feature of a combination of high integration and low energy consumption of CMOSs and high driving force and high speed of bipolar transistors, and has a variety of practical applications. CMOS LSIs including BiCMOS LSIs are, however, accompanied by a disadvantage of being liable to a short channel effect as smaller CMOSs are used. This effect is believe to be principally a function of the degree of extension of the diffusion layers of the source and drain regions of the device. The CMOS LSI device needs to be heat-treated at relatively low temperature to suppress the short channel effect. As a popular practice for reducing the cost of manufacturing a CMOS LSI, a same polysilicon film is often used as a second polysilicon layer for both the emitter electrode and the wired layer of the LSI. As the polysilicon layer is oxidized with time at the surface, the native oxide film formed between the polycrystalline silicon and the silicon substrate supporting the polysilicon layer grows to increase the contact resistance between them. It is also a popular practice to inject an impurity substance into the polycrystalline silicon and heat treat it at high temperature to destroy the native oxide film.
FIG. 1 of the accompanying drawings is a schematic sectional view of a principal area of a conventional BiCMOS semiconductor device. A pair of buried n.sup.+ regions 2 are formed on a p-type silicon substrate to produce a p-channel MOSFET and a bipolar transistor, while a buried p+ region 3 is also formed on the substrate to produce an n-channel MOSFET. Then, a thin n-type epitaxial layer 4 is formed on the substrate. An n well 6 and a p well 5 are formed in the epitaxial layer 4. Thereafter, a deep n.sup.+ region 12 extending from the surface of the epitaxial layer 4 to the n.sup.+ region 2 is formed for the bipolar transistor of the device. Then, the functional elements of the device are isolated from one another. The operation of isolation is carried out by selectively forming thick field oxide film regions 7 on the surface of the wafer and subsequently channel stopper regions (not shown) in respective areas of the epitaxial layer 4 located under the respective field oxide film regions 7. The field oxide film regions 7 and the corresponding respective channel stopper regions are self aligned so as to minimize the overall area of the field oxide film regions 7. As the result of the operation of isolation, a plurality of regions are defined to produce various functional elements of the device including a p-channel MOSFET (hereinafter referred to as PMOS), an n-channel MOSFET (hereinafter referred to as NMOS) and a bipolar transistor.
After removing the native oxide film to expose the surfaces of the regions of the functional elements of the device, the silicon substrate is oxidized to form a silicon oxide (SiO.sub.2) film (not shown) having a thickness approximately between 50 and 200 angstroms (hereinafter expressed as .ANG. that operates as a dummy gate oxide film). Thereafter, ions are injected into the N- and PMOS, or the wells 5 and 6, to give them respective predetermined impurity concentrations. Thus, the N- and PMOS come to show respective threshold voltages. After removing the dummy gate oxide film, a real gate oxide film is formed and then gate electrodes 13 are formed thereon. The first polysilicon layer is used for the gate electrodes. Since the polysilicon electrodes are capable of aligning themselves to the respective source/drain regions to be subsequently formed, such an arrangement is particularly advantageous for an enhanced degree of integration. More specifically, the polysilicon electrode is typically produced by forming an undoped polysilicon film on the semiconductor substrate, diffusing phosphorus into the undoped polysilicon film to a high concentration and transforming it into an n-type layer and etching the film with precision by means of a reactive ion etching technique or a similar high precision technique. Since the gate electrodes 13 are also used as a wired layer, the use of a layer of a silicide obtained by using a metal such as W, Mo, Ti, Pt, Ni or Co or a two layered structure including a silicide layer and a polysilicon layer obtained by causing any of the above mentioned metals and polysilicon to react with each other may be recommended.
P.sup.+ and n.sup.+ source/drain regions 8 and 9 are formed by using the gate electrodes 13 and the field oxide film regions 7 as masks and injecting ions into respective regions. When injecting ions of an n type impurity substance into the NMOS region 5 to produce n.sup.+ source/drain regions 9, the PMOS region 6 and the bipolar transistor region 4 are masked by a photoresist layer. When, on the other hand, injecting ions of a p-type impurity into the PMOS region 6 to produce p+ source/drain regions 8, the NMOS region 5 and the bipolar transistor region 4 are also masked by a photoresist layer. Arsenic (As) is typically used as an n-type impurity, whereas B or boron fluoride is used as a p-type impurity. In order to improve the reliability of the NMOS, a low concentration impurity-diffused region (n.sup.- region) is often formed adjacent to a high concentration impurity-diffused region (n.sup.+ region) to transform the source/drain regions into lightly doped drain source (LDD) regions. The n.sup.- region reduces the potential level of any high potential electric fields that may be generated in the vicinity of the n.sup.+ drain regions and suppresses the generation of hot carriers. Thereafter, a p-type base region is formed on the bipolar transistor.
After producing the impurity-diffused regions, the surface of the wafer including the areas of the gate electrodes 13 is covered by an insulation film 14. A multi-layer film including a non-doped CVDSiO.sub.2 film and a phosphorus glass film such as a phosphosilicate glass (PSG) film or a borophosphosilicate glass (BPSG) film is normally used for the insulation film 14. Since the fluidity of a phosphorus glass film can be modified by heat treatment depending on the extent of phosphorus doping, it is advantageously used to provide a flat surface to LSI devices. Additionally, since a phosphorus-glass film getters harmful alkali metal ions, it can also be utilized as a passivation film. Contact holes 16, 15 are appropriately formed in respective areas of the insulation film 14 that cover the N- and PMOS regions 5 and 6 in order to partially expose the source/drain regions 9 of the NMOS region 5 and the internal base region 11 of the PMOS region 4. Then, a second polysilicon layer is deposited on the insulation film 14 and, thereafter, both an emitter electrode 17 that contacts the internal base region 11 via the contact hole 15 of the bipolar transistor region 4 and a polysilicon wired layer 18 connected to the source/drain regions 9 of the NMOS region 5 via the contact hole 16 are formed by means of an ordinary photography technique. Then, As ions are injected into the polysilicon wired layer 18 and the polysilicon emitter electrode 17 to a high concentration. Subsequently, an interlayer insulation film (not shown) of BPSG is formed on the semiconductor substrate to cover the polysilicon wired layer 18 and the emitter electrode 17. Thereafter, the interlayer insulation film is made to reflow at approximately 900.degree. C. and As ions contained in the emitter electrode 17 are diffused into the internal base region 11, to which an external base region 10 is directly connected, to produce an emitter region 22 there. Then, the device is subjected to a series of work steps including AI wiring and formation of a passivation film.
As described above, in a conventional process of manufacturing a semiconductor device, or an LSI, As ions are injected into both the emitter electrode region and the wired layer regions made of a polysilicon film. Now, since the heat treatment operation of diffusing the impurity substance contained within the emitter electrode region is conducted at approximately 900.degree. C., the wired layer regions and the active region of the semiconductor substrate are put into an excellent contact condition with respect to each other and a high performance bipolar transistor is realized by making the emitter region rather shallow. On the other hand, however, as the semiconductor device is down-sized to show a minimum gate length of less than 0.5 .mu.m in the CMOS, the heat treatment temperature will need to be lowered to less than approximately 850.degree. C. in order to avoid a short channel phenomenon and other undesirable phenomena that may appear when the heat treatment is carried out at a temperature higher than 900.degree. C. Additionally, since the contact area will become less than 0.8.times.0.8 .mu.m.sup.2 it will be extremely difficult to destroy the native oxide film that may be formed to a thickness of 10 to 20 .ANG. on the source/drain regions of the n-type structure such as NMOS. In order to solve this problem, phosphorus which has a remarkable effect of destroying native oxide film may additionally be injected into the polycrystalline silicon of the wired layer. A native oxide film that has been formed on the base p.sup.- -type region of the emitter electrode normally has a thickness between 5 and 12 .ANG. and can be easily destroyed by using any appropriate impurity substance.
On the other hand, when phosphorus is used as an impurity injected into the emitter electrode, it cannot produce a shallow emitter region because of its high thermal diffusion coefficient and the use of phosphorus can result in a poor performance of the bipolar transistor.